Field-programmable gate arrays (FPGAs) provide a variety of memory blocks with various sizes and widths. FPGAs provide a fixed number of each type of memory block, so a given user design may be limited either by the amount of memory or logic required. Some FPGAs include the ability to use logic resources either as logic or as small memories (look-up table random access memory or LUT RAM). This provides a more flexible tradeoff, because LUT RAM blocks can be used either as logic or memory, providing the ability to balance usage of the blocks and giving a more efficient implementation.
Similarly, conventional structured cell arrays (also known as structured application-specific integrated circuits or structured ASICs) provide a fixed number of logic and memory blocks for the user design, but do not provide a resource that can be used as both. Structured ASICs generally provide a lower non-recurring cost compared to gate array or standard cell ASICs by providing a logic cell that contains a number of logic components and that can be configured as well as routed using a small number of mask layers, principally metal and vias. It is known from FPGA architecture that providing a multi-function resource that can act as either memory or logic can provide significant area reduction compared to architectures that provide only heterogeneous single-function resources. A CAD flow to support efficient mapping of user designs into a mix of LUT RAM and hard memories has been reported (see Ahmed et al. U.S. patent application Ser. No. 11/486,564, filed Jul. 13, 2006), as well as efficient methods for implementing multi-function blocks to support LUT RAM (see Lewis et al. U.S. Pat. No. 7,084,665 and Lewis et al. U.S. patent application Ser. No. 11/320,253, filed Dec. 27, 2005). Although a block that can serve two functions may not be as area-efficient at either purpose as a single-purpose block, the ability to implement two different functions leads to improved overall efficiency because of the variation in the number of blocks of each type required by the set of user designs that are implemented. The lower block-level efficiency therefore makes dual-purpose blocks more attractive for smaller memories, while larger memories may still be preferably implemented as hard blocks.